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Mechanical lapping of ultra-thin wafers for 3D integration

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6 Author(s)
S. Pinel ; Lab. d'Analyse et d'Archit. des Syst., CNRS, Toulouse, France ; J. Tasselli ; J. P. Bailbe ; A. Marty
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This paper presents a new technique for thinning down up to 10 μm and handling various semiconductor devices, and transferring them onto host substrates. An optimized mechanical lapping is used to remove the wafer

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Microelectronics, 2000. Proceedings. 2000 22nd International Conference on  (Volume:2 )

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