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An on-chip dynamically recalibrated delay line for embedded self-timed systems

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4 Author(s)
Taylor, G. ; Comput. Lab., Cambridge Univ., UK ; Moore, S. ; Wilcox, S. ; Robinson, P.

Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefits of self-timed design. This paper presents the design of a delay line which may be used to control the timing of an off-chip interface. Timing accuracy is maintained by periodically recalibrating against a low frequency reference clock. The design uses two delay lines so that one can be recalibrated while the other is in use. Recalibration is undertaken once each second; power consumption is low as the calibration circuitry is dormant most of the time. A particular implementation of the design is presented which is suitable for a standard cell or FPGA technology together with experimental performance figures. The paper concludes with some remarks about possible applications in low-power synchronous design

Published in:

Advanced Research in Asynchronous Circuits and Systems, 2000. (ASYNC 2000) Proceedings. Sixth International Symposium on

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