Cart (Loading....) | Create Account
Close category search window
 

A modular fault-tolerant binary tree architecture with short links

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Singh, A.D. ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; Hee Yong Youn

The authors present a novel modular fault-tolerant binary tree architecture which is shown to be more effective in overcoming both operational faults and fabrication defects than earlier approaches. Furthermore, for practical size trees of up to eight levels, it is shown how the proposed design can be efficiently load out in VLSI with very short interconnections. Thus, the design is suitable for monolithic implementation of a large binary tree architectures. For board level multichip designs, a hybrid scheme, combining the new design with the SOFT approach, is presented. It shows better reliability than either design alone

Published in:

Computers, IEEE Transactions on  (Volume:40 ,  Issue: 7 )

Date of Publication:

Jul 1991

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.