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A non-scan DFT method at register-transfer level to achieve complete fault efficiency

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4 Author(s)
S. Ohtake ; Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan ; H. Wada ; T. Masuzawa ; H. Fujiwara

This paper presents a non-scan design-for-testability (DFT) method for VLSIs designed at register transfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods to the controller and the data path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000