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Performance sensitivity analysis using statistical methods and its applications to delay testing

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5 Author(s)
Jing-Jia Liou ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Krstic, A. ; Kwang-Ting Cheng ; Mukherjee, D.A.
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The performance of deep submicron designs can be affected by various parametric variations, manufacturing defects, noise or modeling errors that are all statistical in nature. We propose a statistical framework for analyzing the performance sensitivity of designs to various timing related defects/noise/variations. The core engine of our approach is a highly efficient statistical timing analysis tool. We describe the application of our framework for delay fault modeling and analysis of resistive opens and shorts and as well as interconnect crosstalk. We present experimental results demonstrating the accuracy of our statistical framework as compared to SPICE (for a given set of input patterns) and nominal worst-case analysis, Experimental results for analysis of resistive opens and shorts are also included.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000