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Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

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2 Author(s)
M. Pedram ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Xunwei Wu

This paper presents our research results on power-clocked CMOS design. First we provide algebraic expressions and describe the properties of clocked signals. Next two types of power-clocked CMOS circuit constructions are introduced and analyzed in detail. Since the adiabatic switching requires slow-ramping of the power-clock, a clocked transmission gate and a four-stage clocked NP-domino circuit are presented which receive trapezoidal and sinusoidal power-clocks, respectively. PSPICE simulations demonstrate the correct operation and energy-saving advantage of the proposed circuits.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000