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A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration

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1 Author(s)
K. Ito ; Dept. of Electr. & Electron. Syst., Saitama Univ., Urawa, Japan

In the era of deep submicron technology, wire delay on an LSI chip is becoming relatively larger than operation delay. Increase of execution speed by parallel processing may be limited due to the data transfer time between functional units, If we can dynamically reconfigure nearby functional units into desired operation type and execute operations on the reconfigured units, long data transfer is reduced and hence fast processing can be achieved. In this paper we propose a scheduling method to determine static operation execution time and functional unit allocation to achieve fast signal processing by considering dynamic reconfiguration of functional units. Results show the effectiveness of the proposed method.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000