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Low-power design methodology and applications utilizing dual supply voltages

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2 Author(s)
Usami, K. ; Dept. of Design Methodology, Toshiba Corp., Kawasaki, Japan ; Igarashi, M.

This paper describes a gate-level power minimization methodology using dual supply voltages. Gates and flip-flops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dual-V/sub DD/ circuit synthesis and P&R. We give a brief overview on existing low-power EDA technologies as background and discuss advantages and challenges of the dual-V/sub DD/ approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at negligible area overhead.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000