By Topic

A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system ASCA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kawaguchi, T. ; Dept. of Comput. Sci., Keio Univ., Yokohama, Japan ; Suzuki, T. ; Amano, H.

We describe a floating point arithmetic unit (FPU) which supports static scheduling by automatic parallelizing compiler. This FPU designed to work with 50 MHz clock with the assistance of EDA synthesis and layout tools. Under the clock rate condition, it appears that this FPU requires about 120,000 gates and marks 8.2 MFLOPS with the clock level simulations.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000