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Reconfigurable synchronized dataflow processor

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6 Author(s)
H. Sasaki ; Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; H. Maruyama ; H. Kobayashi ; T. Nakamura
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This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.

Published in:

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference:

9-9 June 2000