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Design of self-timed asynchronous Booth's multiplier

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4 Author(s)
Tin-Yau Tang ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong ; Chiu-Sing Choy ; Pui-Lam Siu ; Cheong-Fat Chan

This paper presents a design of multiplier for the multiplication of two 8-bit two-complement numbers. The multiplier applies the self-timed asynchronous methodology such that the multiplier can be assumed to operate on average case delay. Also, modified Booth's algorithm is used to reduce the number of partial products generated. As a result, the speed of the multiplier can be improved.

Published in:
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Date of Conference: 9-9 June 2000

Page(s):
15 - 16
Meeting Date :
25 Jan 2000-28 Jan 2000
Print ISBN:
0-7803-5973-9
INSPEC Accession Number:
6596960
Conference Location :
Yokohama, Japan
Digital Object Identifier :
10.1109/ASPDAC.2000.835056
Product Type:
Conference Publications

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