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We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-based contention algorithm is proposed, modeling in VHDL for high-speed cell scheduler of ATM switching. A digital Hopfield neural cell scheduler which has the ability of real-time processing is used to solve loss of throughput due to head-of-line (HOL) and internal blocking when FIFO queueing is employed at the Banyan network. In this scheduler, it is found we can minimize the delay for scheduling and select nonblocking cells leading to high performance. Our proposed ATM switch is modeled in VHDL, synthesized, implemented into an FPGA chip set and fabricated using 0.6 /spl mu/m CMOS technology.