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Design, implementation and evaluation of an explicit rate allocation algorithm in an ATM switch

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5 Author(s)
Muthukrishnan, R. ; Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA ; Dasgupta, S. ; Varma, A. ; Kalampoukas, L.
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We discuss a hardware implementation of an explicit rate allocation algorithm for support of available bit rate (ABR) service in ATM switches. We then demonstrate the effectiveness of the algorithm at the network-level through measurements on the actual implementation in a network testbed. The rate allocation algorithm has several desirable properties, such as exact computation of the max-min rates, O(1) computations per resource management (RM) cell received, and the ability to provide minimum cell rate (MCR) guarantees. We show that the algorithm can be implemented with a modest amount of hardware (64,000 gates in an Altera 10K100 programmable logic device and 16 bytes of SRAM storage per VC), and that even a slow FPGA-based implementation with a 20 MHz internal clock rate can process RM cells within one cell time at an OC-3 port. We also outline the design for supporting OC-12 and OC-48 links. We present results from measurements of ABR traffic in network configurations with up to four bottlenecks and 100 connections. The results show that the algorithm is able to converge to the exact max-min fair allocations with no oscillations after convergence, maintains minimum rate guarantees, and is also able to maintain high link utilization in the presence of on-off traffic

Published in:

INFOCOM 2000. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings. IEEE  (Volume:3 )

Date of Conference:

26-30 Mar 2000

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