Skip to Main Content
Systems will rely increasingly on the effective and efficient use of pre-designed intellectual property (IP) cores. Power consumption, unlike speed and area, is much more difficult to predict at a higher level due to its reliance an the circuit level layout. This paper presents a characterization of multiplier blocks for an IP design flow. The paper shows how the blocks vary with respect to operating speed, wordlength and target application. It is shown using the design of a two dimensional discrete cosine transform (DCT), how IP component selection effects circuit power consumption.