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Fast and scalable priority queue architecture for high-speed network switches

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2 Author(s)
Bhagwan, R. ; Center for Wireless Commun., California Univ., San Diego, La Jolla, CA, USA ; Bill Lin

In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine grained quality of service (QoS) guarantees. Priority queues are used to implement highest-priority-first scheduling policies. Our hardware architecture is based on a new data structure called a pipelined heap, or P-heap for short. This data structure enables the pipelining of the enqueue and dequeue operations, thereby allowing these operations to execute in essentially constant time. In addition to being very fast, the architecture also scales very well to a large number of priority levels and to large queue sizes. We give a detailed description of this new data structure, the associated algorithms and the corresponding hardware implementation. We have implemented this new architecture using a 0.35 micron CMOS technology. Our current implementation can support 10 Gb/s connections with over 4 billion priority levels

Published in:

INFOCOM 2000. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings. IEEE  (Volume:2 )

Date of Conference:

2000