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2-D DCT systolic array implementation

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1 Author(s)
Ma, W. ; Dept. of Radio Eng., South China Univ. of Technol., Guangzhou, China

The algorithm and architecture of a 2-D systolic array processor for the DCT (discrete cosine transform) are proposed. It is based on the relationship between DCT and cosine DFT and sine DFT. Two systolic architectures of 1-D DCT data and control flow computation are discussed. By use of the main feature of the two systolic 1-D arrays for DCT, a full 2-D systolic DCT array is presented.

Published in:

Electronics Letters  (Volume:27 ,  Issue: 3 )

Date of Publication:

31 Jan. 1991

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