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Architectures for adaptive weight calculation on ASIC and FPGA

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3 Author(s)
Walke, R.L. ; DERA, Malvern, UK ; Smith, R W M ; Lightbody, G.

We compare two parallel array architectures for adaptive weight calculation based an QR-decomposition by Givens rotations. We present FPGA implementations of both architectures and compare them with an ASIC-based solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost are not critical.

Published in:

Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on  (Volume:2 )

Date of Conference:

24-27 Oct. 1999