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The architectural design and field-programmable logic (FPL) implementation of a digital signal processor (DSP) based on the residue number system (RNS) is presented. This processor makes use of the intrinsic parallelism of RNS for high speed digital signal processing. It consists of a certain number of RNS channels that perform data processing in parallel without any dependency between them. In this way, efficiency is achieved by the reduction in channel word-length. The processor has been modelled at the structural level using VHDL and implemented in Altera FLEX10K devices. Comparison with commercial DSPs for several applications reveals an improvement of up to 133%.