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A design methodology for implementing fast, easily testable arithmetic-logic units (ALUs) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either /spl theta/(N) complexity (Lin-testable) or /spl theta/(1) complexity (C-testable), where N is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lintestable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lintestable ALU is only 0.5%.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:8 , Issue: 2 )
Date of Publication: April 2000