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System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

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4 Author(s)
T. M. Conte ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; K. N. Menezes ; S. W. Sathaye ; M. C. Toburen

This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications. The model of power is novel because it separates power into architectural and technology components. The architectural component is found via trace-driven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is based on case studies of actual designs. It is used to solve an important problem: decreasing power consumption in a superscalar processor without greatly impacting performance. Results are presented from runs using simulated annealing to reduce power consumption subject to performance reduction bounds. The major contributions of this paper are the separation of architectural and technology components of dynamic power the use of trace-driven simulation for architectural power measurement, and the use of a near-optimal search to tailor a processor design to a benchmark.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:8 ,  Issue: 2 )