By Topic

Gate length scalability of n-MOSFETs down to 30 nm: Comparison between LDD and non-LDD structures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
E. Murakami ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; T. Yoshimura ; Y. Goto ; S. Kimura

Gate length scalability of LDD and non-LDD n-MOSFETs are investigated in terms of resistance to short-channel effects. Extremely small gate electrodes are delineated using electron beam direct writing and highly selective dry-etching techniques. An LDD MOSFET with As-implanted 15-nm-deep junctions shows a superior scalability down to 30 nm. In contrast, in the case of a non-LDD MOSFET having Sb-δ-doped 18-nm-deep junctions, the drain induced barrier lowering (DIBL) mechanism limits the minimum gate length to around 80 nm, at which favorable device operation is achieved. The difference between built in potential of source/drain junctions (around 0.1 eV) of LDD and non-LDD devices is found to remarkably affect short channel characteristics in the sub-0.1-μm region

Published in:

IEEE Transactions on Electron Devices  (Volume:47 ,  Issue: 4 )