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GaAs MESFET differential pass-transistor logic

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2 Author(s)
Pasternak, J.H. ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada ; Salama, C.A.T.

A GaAs MESFET implementation of differential pass-transistor logic (DPTL) is presented. This logic technique combines the greater area efficiencies and high operation speeds of ratioless, pass-transistor circuits with the additional advantages of good noise immunity and low power dissipation. Experimental results are provided for a four-bit counter implemented in a 1 mu m, depletion (D)-mode MESFET technology to demonstrate both the functionality and noise immunity of GaAs DPTL.

Published in:

Electronics Letters  (Volume:26 ,  Issue: 19 )