By Topic

Signal margin test to identify process sensitivities relevant to DRAM reliability and functionality at low temperatures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Nelson, E. ; IBM Microelectron., Essex Junction, VT, USA ; Li, Y. ; Poindexter, D. ; Ruprecht, M.
more authors

With high aspect ratio, tight spacing, small line widths, and low supply voltages associated with the scaling of the DRAM cell, signal for the sense amplifier becomes weaker for each new DRAM generation. We have developed a signal margin testing methodology capable of identifying process sensitivities relevant to DRAM functionality and reliability at low temperatures. This paper describes the test methodology and discusses the benefits derived from applying this method to 256M DRAM product development

Published in:

Integrated Reliability Workshop Final Report, 1999. IEEE International

Date of Conference:

1999