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A high-performance ATM switch with multicasting

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2 Author(s)
Ho, J.D. ; Sch. of Comput. Sci. & Comput. Eng., La Trobe Univ., Bundoora, Vic., Australia ; Sharma, N.K.

This paper presents an ATM switch that fulfills the architectural and service requirements of large-scale ATM switches. The proposed network is based on a 3-stage Clos network, with shared-memory ATM switches at the input and output stages to provide optimal cell loss and delay performance. Unlike other Clos based networks, this paper proposes a simple distributive routing algorithm for any sized network. Distributive multicasting allows multiple multicast cells to be routed simultaneously through the network, which removes the problem of multicast congestion. The performance of shared-memory switches can be further improved by implementing a buffer management scheme. The proposed write and read policies can adapt to changes in traffic, so an optimum unicast/multicast mix can be maintained. In total, the proposed ATM switch delivers the characteristics required for future ATM services

Published in:

Global Telecommunications Conference, 1999. GLOBECOM '99  (Volume:2 )

Date of Conference:

1999