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Optimised design for a 0.5 mu m gate length n-channel SOI MOSFET

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2 Author(s)
G. A. Armstrong ; Dept. of Electr. Eng., Queen's Univ. of Belfast, UK ; W. D. French

Two dimensional device simulation has been used to optimise the design of an n-channel silicon-on-insulator MOSFET with an ultra thin film. The trade-off between SOI film thickness and film doping on the threshold voltage, inverse subthreshold slope and breakdown voltage is considered. The effect of carrier lifetime on the breakdown voltage is described. Use of a lightly doped drain gives a simulated breakdown voltage greater than 3..5 V for a transistor with a film thickness of 1000 AA and a gate length of 0.5 mu m.

Published in:

Electronics Letters  (Volume:26 ,  Issue: 15 )