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Timing optimization on routed designs with incremental placement and routing characterization

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3 Author(s)
Chieh Changfan ; Dept. of Comput. Sci., California Univ., Riverside, CA, USA ; Yu-Chin Hsu ; Fur-Shing Tsai

Wire delay estimation has been a problem in designs of very deep submicron (VDSM) technologies with feature size under 0.25 μm. The conventional back-annotation approach does not guarantee timing convergence due to different estimation techniques for prelayout and post-layout timing. In this paper, a post-routing timing optimization algorithm is presented. Experimental results show that this algorithm provides better result after detail routing is completed

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:19 ,  Issue: 2 )