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This paper presents the architecture and implementation of a highly versatile beamforming ASIC (VBASIC) for application in broad-band fixed wireless access systems. The architecture accommodates a large number of user-programmable parameters, which broaden the chip's application base to a variety of present and future systems for fixed wireless access. These features include: (a) a novel structure for variable-rate interpolation that allows operation at any user specified symbol rate from 625 kBaud to 10 MBaud; (b) operation in both the transmit and receive modes; (c) support for arrays consisting of up to 64 elements; (d) a unique shaping filter structure with programmable canonic signed digit coefficients; (e) complete reconfiguration of all parameters on a per-time-slot basis; and f) digital intermediate-frequency interface. The resulting layout measures 7.1 mm on each side in the 0.6-/spl mu/m HPCMOS14 process and consists of a total of 787 987 transistors.
Date of Publication: March 2000