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Low-power direct digital frequency synthesis for wireless communications

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4 Author(s)
Bellaouar, A. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; O'brecht, M.S. ; Fahim, A.M. ; Elmasry, M.I.

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-/spl mu/m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 3 )