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An architecture for efficiently implementing linear and nonlinear Viterbi detectors for magnetic read channels is presented. By employing generalized noiseless target values for the Viterbi trellis, the detector is better able to adapt to the actual binary data storage channel and less equalization is needed, resulting in a significant reduction in the probability of error. An implementation example is presented for the case of a 16-state Viterbi detector having a capability of handling any noiseless target of up to five adjacent nonzero values. In a 0.6 /spl mu/m (drawn) 3.0 V CMOS process, the design has been implemented with a die area of 9 mm/sup 2/ consuming under 350 mW of power when operated at 110 MHz.