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A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR

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4 Author(s)
Fogelman, E. ; Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA ; Galton, I. ; Huff, W. ; Jensen, H.

This paper presents a second-order /spl Delta//spl Sigma/ modulator for audio-band analog-to-digital conversion implemented in a 3.3-V, 0.5-/spl mu/m, single-poly CMOS process using metal-metal capacitors that achieves 98-dB peak signal-to-noise-and-distortion ratio and 105-dB peak spurious-free dynamic range. The design uses a low-complexity, first-order mismatch shaping 33-level digital-to-analog converter and a 33-level flash analog-to-digital converter with digital common-mode rejection and dynamic element matching of comparator offsets. These signal-processing innovations, combined with established circuit techniques, enable state-of-the art performance in CMOS technology optimized for digital circuits.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 3 )