By Topic

A CAD environnnent for digital filters using a VerilogHDL based functional bit-serial compiler

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Eminoglu, S. ; Middle East Tech. Univ., Ankara, Turkey ; Akin, T.

This paper reports the development of a highly integrated CAD environment for area efficient implementation of digital filters using commercially available CAD tools. The environment establishes a plain interface between CADENCE (an IC design framework), MATLAB (a mathematical computation tool), and BITMAP (a new custom-developed filter compiler). The new compiler allows the functional description of the target filter in the Verilog hardware description language (VerilogHDL), generating technology independent and retargetable digital filters in the bit-serial architecture. This integrated design environment shortens the implementation time, reduces the number of gates, and minimizes the overall filter area. The CAD environment and the new functional compiler have been used to implement a mixed-signal ASIC chip with thirteen digital IIR and FIR filters, three pairs of over sampled A/D and D/A converters, parallel port and I2C type microprocessor interfaces, and a number of analog interface circuits. The chip occupies an 81 mm2 area in a 0.7 μm CMOS technology

Published in:

Microelectronics, 1998. ICM '98. Proceedings of the Tenth International Conference on

Date of Conference: