Noise-tolerance analysis for high speed CMOS circuits

The noise tolerance of new submicron logic families is becoming more and more important for the reliability of high speed architectures. A method for the evaluation of noise robustness must be defined to compare different topologies and help designers in the library cells optimization, The paper describes a methodology for the analysis of self induced noise tolerance based on the statistical simulation of noise sources. This method can be usefully applied in the study of parasitics due to interconnections crosstalk in digital design and to the substrate-coupling in ICs.