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Static scheduling for out-of-order instruction issue processors

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3 Author(s)
Tate, D. ; Dept. of Comput. Sci., Hertfordshire Univ., Hatfield, UK ; Steven, G. ; Steven, F.

Superscalar processors strive to increase the number of instructions issued in each processor cycle. Compilers therefore need to expose as much Instruction Level Parallelism (ILP) as possible by using increasingly complex code optimisations. However, the knowledge base of instruction scheduling is focused on in-order instruction issue. It has previously been determined that aggressive static instruction scheduling impedes the speedup achieved by out-of-order instruction issue given an ideal environment. This paper examines how the scheduling process impairs the performance of out-of-order instruction issue. The use of Boolean guards, function in-lining, register renaming and percolation both between basic blocks and around loop back edges is evaluated. The results show that removing Boolean guards and severely limiting percolation while retaining function in-lining produces an improvement over unscheduled benchmarks

Published in:

Computer Architecture Conference, 2000. ACAC 2000. 5th Australasian

Date of Conference:

2000

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