Referenced Items are not available for this document.
A novel architecture for reconfigurable computing based on a coarse grain FPGA-like architecture is introduced. The basic blocks contain all arithmetical and logical capacities as well as some registers and will be programmable by sequential instruction streams produced by software compiler. Reconfiguration is related to hyper-blocks of instructions. For the composed reconfigurable processors a classification is introduced for describing realtime, multithreading and performance capabilities
Published in:
Computer Architecture Conference, 2000. ACAC 2000. 5th Australasian
Date of Conference: 2000
- Page(s):
- 82 - 89
- Meeting Date :
- 31 Jan 2000-03 Feb 2000
- Print ISBN:
- 0-7695-0512-0
- INSPEC Accession Number:
- 6483801
- Conference Location :
- Canberra, ACT
- Digital Object Identifier :
- 10.1109/ACAC.2000.824328
- Product Type:
- Conference Publications
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