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Intra-field gate CD variability and its impact on circuit performance

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6 Author(s)
M. Orshansky ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; L. Milor ; Ly Nguyen ; G. Hill
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Statistical analysis of an advanced CMOS process reveals a significant systematic within-field variability of gate CD strongly dependent on the local layout patterns. We present a novel modeling methodology for accurate prediction of the effect of such CD variability on circuit performance that enables statistical design for increased performance and yield. We also propose a mask-level gate CD correction algorithm allowing significant reduction of overall variability and provide a model to evaluate the effectiveness of correction.

Published in:

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Date of Conference:

5-8 Dec. 1999