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A high performance DSP architecture “MSPM” for digital image processing using embedded DRAM ASIC technologies

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4 Author(s)
Yoshizawa, H. ; Fujitsu Labs. Ltd., Kawasaki, Japan ; Tsuruta, T. ; Kumamoto, N. ; Kurita, M.

This paper describes the architecture of the “MSPM: Multimedia Signal Processor with embedded Memory”. It has been developed to evaluate the architectural effects of 0.35-micron embedded DRAM technologies on the performance. The chip has achieved 24 times the performance of an ordinary RISC processor at the same frequency, and also ten times the performance of an ordinary 16 bit DSP. The improvement has been made possible by the following architectural characteristics: direct-memory-referring instruction sets; SIMD-type-parallel-executing features; byte-aligned-word-access features; and multi-instruction migrating features. The MSPM achieved 800 MOPS@66 MHz with 1.1 Gbyte/s bandwidth. Integration of a 16 Mb DRAM with 128 bit data bus is also reported

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ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

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