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A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems

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2 Author(s)
Miyazaki, M. ; Central Res. Lab., Hitachi Ltd., Kokubunji, Japan ; Ishibashi, K.

We have developed a delay-locked loop (DLL) which has a parallel phase-detector for generating a system clock in LSIs. The generated clock is synchronized to an internal clock for various loads in a system. The DLL achieves a settling time of 3 clock-cycles and a maximum skew of 150 ps. The operating frequency is from 66 MHz to 230 MHz with a typical power consumption of 13.5 mW at 100 MHz. In addition, due to the short settling time, the DLL can be powered down to reduce the standby current

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ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

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