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High efficient 3-input XOR for low-voltage low-power high-speed applications

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2 Author(s)
Kuo-Hsing Cheng ; Dept. of Electr. Eng., Tamkang Univ., Tamsui, Taiwan ; Ven-Chieh Hsieh

A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications

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ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Date of Conference: