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VLSI architecture for low power motion estimation using high data access reuse

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2 Author(s)
Bo-Sung Kim ; VLSI Algorithmic Design Autom. Lab., SungKyunKwan Univ., Kyunggi-do, South Korea ; Jun-dong Cho

This paper presents a new VLSI architecture of the motion estimation in MPEG-2. Previously various full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have inefficiently a large number of external memory access. Our new architecture efficiently reuses data to decrease external memory accesses and saves the computational time by using a parallel algorithm

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ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Date of Conference: