Referenced Items are not available for this document.
This paper presents a new VLSI architecture of the motion estimation in MPEG-2. Previously various full search block matching algorithms (BMA) and architectures using systolic array have been proposed for motion estimation. However, the architectures have inefficiently a large number of external memory access. Our new architecture efficiently reuses data to decrease external memory accesses and saves the computational time by using a parallel algorithm
Published in:
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Date of Conference: 1999
- Page(s):
- 162 - 165
- Meeting Date :
- 23 Aug 1999-25 Aug 1999
- Print ISBN:
- 0-7803-5705-1
- INSPEC Accession Number:
- 6581925
- Conference Location :
- Seoul
- Digital Object Identifier :
- 10.1109/APASIC.1999.824053
- Product Type:
- Conference Publications
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