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A high-performance low-power asynchronous matrix-vector multiplier for discrete cosine transform

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2 Author(s)
Kyeounsoo Kim ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Beerel, P.A.

This paper proposes a high-performance low-power asynchronous architecture for matrix-vector multipliers of a constant matrix by a vector which are typically used in discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) applications. The architecture takes advantage of the statistics of DCT and IDCT data that suggest that the input data have mostly zero or small values. It avoids unnecessary arithmetic operations by quickly terminating multiplication by zero and significantly reduces power and delay when operating on a small-valued data by adaptively controlling effective word lengths using fine-grain bit-partitioning and speculative completion sensing

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ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

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