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Design and implementation for 125 mW/MIPS ultra-high speed low power asymmetric digital subscriber line transceiver chip

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5 Author(s)
Seong-Jo Na ; Dept. of Inf. & Commun. Eng., Dongshin Univ., Chonnam, South Korea ; M. M. -O. Lee ; Tin-Hong Chung ; Seung-Min Lee
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Multimedia service with audio and video have become most desirable as the ADSL technology ideally converted from 1.5 Mbps full duplex HDSL technology via two twist-pair into 6.144 Mbps transmission technology via single twist-pair. This results in an interactive transmission service of T1 & E1 class data using the subscriber line without repeaters. The ADSL transceiver chipset is configured by DMT (Discrete Multi Tone modulation) scheme and RISC-based DSP core structure. Our ADSL chip is to be used in VOD, interactive interact service and/or teleconferencing system, etc. The operating frequency and dissipated power of the chip are 40 MHz and 5 W at 5 V

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ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

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