Thermally robust dual-gate CMOS integration technologies for high-performance DRAM-embedded ASICs

We have demonstrated three key integration technologies of thermally stable dual-gate CMOSFETs for DRAM-embedded ASICs. These technologies include: (1) a thermally stable W-polycide gate for every MOSFET and CoSi/sub 2/ diffusion for logic CMOS to maintain low resistance, (2) nitrogen implantation into WSi/sub 2/ to prevent lateral dopant diffusion without gate depletion, and (3) a Si/sub 3/N/sub 4//TEOS-BPSG stacked interlayer for self-aligned contacts (SAC) without boron penetration in PMOSFETs. High-performance CMOSFETs using these technologies and 5 metal layers result in a flexible circuit design which can achieve 6.8 ns access speed in a 64 Mb DRAM-embedded macro with a 0.25 /spl mu/m design rule.