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A 1.0-GHz 0.6-μm 8-bit carry lookahead adder using PLA-styled all-N-transistor logic

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3 Author(s)
Wang, C.-C. ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Chenn-Jung Huang ; Kun-Chu Tsai

This article presents a high-speed 8-bit carry-lookahead adder (CLA) using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor (ANT) blocks which are arranged in a programmable logic array design style. Detailed simulation reveals appropriate L/W guidelines for the ANT block design. The area (transistor count) tradeoff is also analyzed. The operating clock frequency is 1.0 GHz, while the output of the addition of two 8-bit binary numbers is completed in two cycles. Simulation results confirm that the proposed design methodology is appropriate for the long adders, e.g., 64-bit adders, while the correct output is available after four cycles if the 64-bit adder is composed of nine hierarchical 8-bit CLA's

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 2 )

Date of Publication:

Feb 2000

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