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A mixed-signal integrated circuit implements 1120 analog memory points arranged in 16 independent fully programmable delay lines in a 0.8 /spl mu/m CMOS technology. It demonstrates the feasibility of large scale mixed-mode circuits using the switched current technique. The die area of the chip is 72 mm/sup 2/ and incorporates 16 rather large and complex analog blocks, which take advantage of special design techniques developed in order to keep power consumption at a reasonable level and to eliminate second-order effects due to long power and signal lines. At the nominal 64 MHz sampling rate, harmonic distortion is -48 dB, dynamic range is above 60 dB, and power consumption is 1.22 W from a single 5 V supply.