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An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures

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4 Author(s)
Koziris, N. ; Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Greece ; Romesis, M. ; Tsanakas, P. ; Papakonstantinou, G.

The most important issue in sequential program parallelisation is the efficient assignment of computations into different processing elements. In the past, too many approaches were devoted in efficient program parallelization considering various models for the parallel programs and the target architectures. The most widely used parallelism description model is the task graph model with precedence constraints. Nevertheless, as far as physical mapping of tasks onto parallel architectures is concerned little research has given practical results. It is well known that the physical mapping problem is NP-hard in the strong sense, thus allowing only for heuristic approaches. Most researchers or tool programmers use exhaustive algorithms, or the classical method of simulated annealing. This paper presents an alternative approach onto the mapping problem. Given the graph of clustered tasks, and the graph of the target distributed architecture, our heuristic finds a mapping by first placing the highly communicative tasks on adjacent nodes of the processor network. Once these “backbone” tasks are mapped there is no backtracking, thus achieving low complexity. Therefore, the remaining tasks are placed beginning from those close to the “backbone” tasks. The paper concludes with performance and comparison results which reveal the method's efficiency

Published in:

Parallel and Distributed Processing, 2000. Proceedings. 8th Euromicro Workshop on

Date of Conference:

2000