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Improved system design through proper nesting of test levels

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1 Author(s)
Patterson, J. ; AT&T Bell Labs., North Andover, MA, USA

The author presents a methodology, for use early in the system design cycle, that improves yields and reduces time until volume production. It identifies simultaneous, mutually consistent, and properly nested electrical requirements at the system, circuit module, and component device levels. The proposed approach involves a checklist framework for the test compatibility methodology and a graph that helps to identify a confidence level for individual tests. The checklist identifies six lo/hi limit pairs based on different test levels that are directly comparable with each other and that are concise enough to fit into a table. The graph clearly shows the need for more than 3-sigma confidence levels. Over four independent 3-sigma tests in a module test result in more than 1% dropout

Published in:

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Date of Conference:

29-31 Aug 1989