Asynchronous transfer mode (ATM) technology offers many technical advantages to the military user and is of great interest to the military for their future army communication requirements. One of the many challenges being faced when using ATM in the military arena is improving its robustness and performance at bit error rates (BER) of 10-5 and higher. These BER rates are inherent to military wireless links. Many “link adaptation” schemes have been modeled with various error profiles; these have given invaluable error performance figures showing how ATM may survive on an error prone link. Our interest lay in designing a generic testbed of flexible architectures to enable us to try out various schemes in real environments with minimal engineering overheads and gain real results. This paper discusses the thinking behind the design methodology, the architectures used for implementation and the final “scheme” chosen for proof of concept testing
Published in:
Military Communications Conference Proceedings, 1999. MILCOM 1999. IEEE
(Volume:1
)
Date of Conference: 1999