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Matching analysis of NMOS-transistors with a channel length down to 30 nm

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3 Author(s)
Horstmann, J.T. ; Fac. of Electr. Eng., Dortmund Univ., Germany ; Hilleringmann, U. ; Goser, K.

NMOS-transistors with a gate length down to 30 nm are fabricated applying a modified deposition- and etchback-technique for gate definition using only conventional optical lithography. This leads to an excellent homogeneity and uniformity of the channel length which enables a trustworthy statistical analysis of the transistors. The influence of the inevitable statistical fluctuations of the channel doping on the fluctuations of the electrical device characteristics is examined. This local and global matching of the transistors with dimensions varying from W/L=10 μm/1 μm down to W/L=1 μm/30 nm is analyzed by a large number of measurements. The results are compared to the law of area (σVT∝1/√(W·L)) showing a good agreement even for the smallest geometries

Published in:

Industrial Electronics Society, 1999. IECON '99 Proceedings. The 25th Annual Conference of the IEEE  (Volume:1 )

Date of Conference:

1999