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A four-transistor CMOS SRAM cell

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3 Author(s)
Joubert, T.-H. ; Dept. of Electr. & Electron. Eng., Pretoria Univ., South Africa ; Seevinck, E. ; du Plessis, M.

In CMOS, an SRAM cell containing six transistors is generally used. If a smaller number of transistors and fewer connection lines were possible, the packing density of SRAM chips may be improved. A reduce-area four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed in this paper

Published in:

Africon, 1999 IEEE  (Volume:2 )

Date of Conference:

1999