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W CMP evaluation for 0.25 μm logic device

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7 Author(s)
Jong-Hyup Lee ; Syst. IC R&D Center, Hyundai Electron. Ind. Co. Ltd., Kyoungki, South Korea ; Byoung-Ho Kwon ; Se-Young Lee ; Hee-Jeen Kim
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The purpose of this study is to report polishing characteristics of W CMP with combination sets of slurry and pad in 0.25 um logic technology. W etch back process is compared with W CMP process in view of electrical performance in the 0.25 μm logic device. The proper selection of consumables is important to the successful application of W CMP. The W CMP process should be carefully controlled to be implemented in the back-end process of sub-quarter micron logic device

Published in:

VLSI and CAD, 1999. ICVC '99. 6th International Conference on

Date of Conference:

1999